The present invention relates to ternary content addressable memory (CAM) cells. More specifically, the present invention relates to ternary CAM cells having improved compare and mask circuits.
FIG. 1 is a circuit diagram of a conventional ternary CAM cell system 100, which includes main memory cell 101, compare circuit 102, mask circuit 103, pre-charge circuit 104, mask memory cell 105 and match line 106. Compare circuit 102 includes n-channel transistors 111-113, and mask circuit 103 includes n-channel transistor 114. A data value comprised of complementary data signals D and D# is written to main memory cell 101 on complementary bit lines BL and BL#, respectively. Once written, main memory cell 101 provides complementary data signals D# and D to the gates of transistors 111 and 112, respectively. A mask value (M) is written to mask memory cell 105. The mask value is applied to the gate of n-channel transistor 114 of mask circuit 103.
A compare operation is performed in ternary CAM cell system 100 as follows. Pre-charge circuit 104 applies a positive voltage to match line 106, thereby charging match line 106 to a logic high state. Pre-charge circuit 104 then allows match line 106 to float. A sense amplifier (not shown) senses the state of match line 106. A compare value comprised of complementary data signals C and C# is applied to complementary compare lines CMP and CMP#, respectively, and thereby to the sources of transistors 111 and 112, respectively. If the compare value matches the data value previously written to main memory cell 101, then a logic low signal is applied to the gate of transistor 113. In this case, transistor 113 is turned off, and match line 106 remains at a logic high state, thereby indicating a match condition.
However, if the compare value does not match the data value previously written to main memory cell 101, then a logic high signal is applied to the gate of transistor 113. In this case, transistor 113 is turned on. If transistor 114 is also turned on (i.e., the mask value M is programmed to a logic high value), then match line 106 is pulled down to a logic low state (i.e., ground), thereby indicating a no-match condition.
If the mask value M has a logic low value, then transistor 114 is turned off, and match line 106 will not be pulled down by ternary CAM system 100 regardless of the presence of a match or no-match condition.
Ternary CAM system 100 has the following shortcomings. First, ternary CAM system 100 requires two separate functional blocks to implement the compare and mask functions (i.e., compare circuit 102 and mask circuit 103). As a result, a relatively large number of transistors are required to implement ternary CAM system 100. Second, match line 106 is limited to a logic high pre-charge state.
FIG. 2 is a circuit diagram of another conventional ternary CAM system 200, which includes main memory cell 201, compare circuit 202, mask circuit 203, pre-charge circuit 204, mask memory cell 205 and match line 206. Compare circuit 202 includes n-channel transistors 211-212, and mask circuit 203 includes n-channel transistor 214. A data value comprised of complementary data signals D and D# is written to main memory cell 201 on complementary bit lines BL and BL#, respectively. Once written, main memory cell 201 provides complementary data signals D and D# to the sources of transistors 211 and 212, respectively. A mask value (M) is written to mask memory cell 205. The mask value is applied to the gate of n-channel transistor 214 of mask circuit 203.
A compare operation is performed in ternary CAM cell system 200 as follows. Pre-charge circuit 204 applies a positive voltage to match line 206, thereby charging match line 206 to a logic high state. Pre-charge circuit 204 then allows match line 206 to float. A sense amplifier (not shown) senses the state of match line 206. A compare value comprised of complementary data signals C and C# is applied to complementary compare lines CMP and CMP#, respectively, and thereby to the gates of transistors 211 and 212, respectively. If the compare value matches the data value previously written to main memory cell 201, then a logic high signal is applied to the source of transistor 214. If transistor 214 is turned on (i.e., the mask value M is programmed to a logic high value), a logic high signal is applied to match line 206, thereby indicating a match condition.
However, if the compare value does not match the data value previously written to main memory cell 201, then a logic low signal is applied to the source of transistor 214. If transistor 214 is turned on (i.e., the mask value M is programmed to a logic high value), a logic low signal is applied to match line 206, thereby indicating a no-match condition.
If the mask value M has a logic low value, then transistor 214 is turned off, and match line 206 will not be pulled down by ternary CAM-system 200 regardless of the presence of a match or no-match condition.
Ternary CAM system 200 has the following shortcomings. First, ternary CAM system 200 requires two separate functional blocks to implement the compare and mask functions (i.e., compare circuit 202 and mask circuit 203). Second, during a compare operation, the data value stored in main memory cell 201 can be disturbed by the current flow through compare circuit 202 and mask circuit 203.
It would therefore be desirable to have an improved ternary CAM system that overcomes the deficiencies of conventional ternary CAM systems.
Accordingly, the present invention provides a ternary CAM system that includes a main memory cell, a compare/mask circuit, a mask memory cell, a match line, a pre-charge circuit and a sense amplifier. The pre-charge circuit and the sense amplifier are coupled to the match line. The pre-charge circuit is programmable to pre-charge the match line to either a logic high state or a logic low state, depending on the configuration of the ternary CAM system. The main memory cell stores a data value represented by complementary data signals D and D#. The data signal D# is applied to the source of a first transistor of the compare/mask circuit, and the data signal D is applied to the source of a second transistor of the compare/mask circuit. The gate of the first transistor is coupled to receive a compare data signal C, and the gate of the second transistor is coupled to receive a compare data signal C#, wherein the compare data signals C and C# are complementary signals representing a compare value. The drains of the first and second transistors are coupled to the gate of a third transistor of the compare/mask circuit. The source of the third transistor is coupled to receive a mask value stored in the mask memory cell, and the drain of the third transistor is coupled to the pre-charged match line.
The compare data signals C and C# turn on one and only one of the first and second transistors. If the compare data value matches the data value, then the turned on one of the first and second transistors passes a signal having a first state to the gate of the third transistor, thereby turning off the third transistor. Thus, if the compare data value matches the data value, the match line remains isolated from mask memory cell. The pre-charged match line thereby remains in a pre-charged state.
If the compare data value does not match the data value, then the turned on one of the first and second transistors passes a signal having a second state to the gate of the third transistor, thereby turning on the third transistor. Thus, if the compare data value does not match the data value, the match line is coupled to the mask memory cell through the third transistor. The mask value stored in the mask memory cell may have a state that matches the pre-charged state of the match line, such that the mask memory cell implements a mask function. Alternately, the mask value may have a state that does not match the pre-charged state of the match line, such that the mask memory cell will change the state of the pre-charged match line when the compare data value does not match the data value.
In another embodiment, the compare/mask circuit is configured in a slightly different manner. In this embodiment, the data signal D# is applied to the gate of a first transistor of the compare/mask circuit, and the data signal D is applied to the gate of a second transistor of the compare/mask circuit. The source of the first transistor is coupled to receive a compare data signal C, and the source of the second transistor is coupled to receive a compare data signal C#, wherein the compare data signals C and C# are complementary signals representing a compare value. The drains of the first and second transistors are coupled to the gate of a third transistor of the compare/mask circuit. The source of the third transistor is coupled to receive a mask value stored in the mask memory cell, and the drain of the third transistor is coupled to the pre-charged match line.
The data signals D and D# turn on one and only one of the first and second transistors. If the compare data value matches the data value, then the turned on one of the first and second transistors passes a signal having a first state to the gate of the third transistor, thereby turning off the third transistor. Thus, if the compare data value matches the data value, the match line remains isolated from mask memory cell. The pre-charged match line thereby remains in a pre-charged state.
If the compare data value does not match the data value, then the turned on one of the first and second transistors passes a signal having a second state to the gate of the third transistor, thereby turning on the third transistor. Thus, if the compare data value does not match the data value, the match line is coupled to the mask memory cell through the third transistor. The mask value stored in the mask memory cell may have a state that matches the pre-charged state of the match line, such that the mask memory cell implements a mask function. Alternately, the mask value may have a state that does not match the pre-charged state of the match line, such that the mask memory cell will change the state of the pre-charged match line when the compare data value does not match the data value.
Advantageously, the compare/mask circuit only requires three transistors. Moreover, the compare/mask circuit does not draw a current that may disturb the data value stored in the main memory cell during a compare operation. In addition, the match line can be pre-charged to either a low state or a high state by controlling the pre-charge circuit, and programming the mask memory cell with the appropriate mask value.
In one embodiment, the data value is provided to the main memory cell on a first pair of bit lines, and the compare data value is provided to the compare/mask circuit on a second pair of bit lines. In one variation, the first and second pair of bit lines can be consolidated into a single pair of bit lines.
The present invention will be more fully understood in view of the following drawings and description.